(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a process for a FET with TiSi.sub.2 S/D contacts and CoSi.sub.x gate contacts.
(2) Description of the Prior Art
Field Effect Transistors (FET's) have found wide application in the semiconductor industry. The fabrication of a FET typically starts with a single crystal semiconductor substrate; a thin layer of gate oxide is grown over the surface of the substrate. A polysilicon gate is patterned over the thin layer of gate oxide, the gate electrode is then used as a diffusion or implant barrier mask to form self-aligned source and drain areas in the substrate immediately adjacent to the sides of the gate electrode. The region between the source/drain regions is called the channel region, the distance between the source and the drain junction is called the channel length. In its simplest terms of operation, an input voltage is applied to the gate electrode, this voltage establishes an electric field in the channel region of the device, and this electric field is perpendicular to the surface of the substrate and the thin layer of gate oxide. By varying the value of the applied voltage, the conductance of the channel region can be controlled. Because the electric field that is established by this voltage controls the output current flow through the device, the semiconductor devices created using this approach are called Field Effect Transistors (FET's).
In a typical FET, metal contacts are established with the gate electrode and with the source and the drain regions of the transistor. This can be done by sputtering a layer of refractory metal over the exposed surface of these areas. By heating this layer of metal (typically titanium, tantalum, platinum, nickel or cobalt) to a temperature of between 200 and 850 degrees C., a self-aligned salicide region is formed on top of the gate electrode and on the source and drain regions.
Prior to the deposition of the above indicated layer of metal, contact holes to the source/drain regions have to be opened through the thin layer of gate oxide. As transistor dimensions have decreased, the conventional contact structures began to limit device performance. It was, for instance, not possible to minimize the contact resistance if the contact hole was of minimum size while problems with cleaning small contact holes became a concern. In addition, the area of the source/drain regions could not be minimized because the contact hole had been aligned to this region using a separate masking step whereby extra area had to be allocated to accommodate misalignment. It was also practice to use several, small contact holes of identical size meaning that the full width of the source/drain region was not available for the contact structure. This resulted in the source/drain resistance being proportionally larger than it would have been in a device having minimum width.
Self-alignment is a technique in which multiple regions on the wafer are formed using a single mask, thereby eliminating the alignment tolerances that are required by additional masks. As circuit sizes decrease, this approach finds more application. One of the areas where the technique of self-alignment was used at a very early stage was the self-aligned source and gate implant to the poly gate.
One of the alternate structures that have been employed in an effort to alleviate the problem of increased source/drain resistance is the formation of self-aligned silicides on the source/drain regions. Where these silicides are formed at the same time as the polycide structure, this approach is referred to as a salicide process. The entire source/drain region (of, for instance, a MOSFET device) is contacted with a conductor film. This approach becomes even more attractive where such a film can be formed using a self-aligned process that does not entail any masking steps.
Continuous shrinkage of the gate length demands low resistivity of the source/drain regions, as well as shallow junctions in the source/drain areas to avoid short channel effect, which is mainly caused by inappropriate dopant distribution underneath the channel region. Shallow junctions greatly help resolve this problem.
Various techniques have been developed for forming the shallow source/drain junctions that are needed for sub-micron CMOS devices. One such approach uses As for the n-channel devices while BF.sub.2.sup.+ is used for the p-channel devices. Yet another approach uses the creation of so-called elevated source-drain. A thin (for instance 0.2 um.) epitaxial layer of silicon can be selectively deposited onto the exposed source/drain areas of the MOS transistor, this following the implantation of the lightly doped region of the LDD structure and the formation of the spacers. This process leads to the formation of heavily doped, shallow source/drain regions. The source/drain junction depths in this case are less than 0.2 um.
FIG. 1 shows Prior Art formation of a gate electrode with contact openings for the source/drain regions. A polysilicon gate structure 24 is formed including the formation of Shallow Trench Isolation (STI) regions 18 between the gate structures. After the source and drain areas 12 and 14 have been implanted to form the source/drain junctions, the sidewall spacers (not shown) are formed. Spacers can be made using silicon-nitride or silicon-oxide, BSG, PSG, polysilicon, other materials preferably of a dielectric nature, CVD oxide formed from a TEOS source. Often used are amorphous materials that inhibit the deposition of epitaxial silicon thereupon.
A thick (2-layer deposition) layer 70 of undoped oxide is deposited over the gate electrode 24, the adjacent STI regions 18 and the exposed surface of the semiconductor substrate 13. Over this layer 70, a layer 72 of boronphosphosilicate glass (BPSG) needs to be added for conventional contacts. Contact holes 26 are opened in layer 72 and layer 70 down to the source/drain regions, these contact openings typically have a width of between 0.20 and 0.30 um.
FIG. 2 shows the effect that exposure to wet cleaning can have on the surface of the STI areas. Gate electrode 24 is shown together with gate spacers 22 and an adjacent STI region 18. The surface 27 of the STI 18 shows two irregularities in the areas 28 and 29 where this surface 27 interfaces with the surface of the semiconductor substrate 13. During the formation of the STI region, the silicon in the areas 28 and 29 can be exposed by wet cleaning. The exposed silicon can be salicided at that time and can therefore cause leakage currents to occur. On the other hand, a thicker silicide layer can result in higher leakage current especially for shallow junction devices.
The salicide process further has a limitation related to the fact that the gate and the source/drain silicides are formed at the same time. On the gate, it is desirable for the silicide to have the lowest possible sheet resistance (so the gate electrode will have a low interconnect resistance). To achieve this, a thick silicide layer is needed. Over the source/drain regions, however, the silicide can only be of limited thickness in order to prevent excess consumption of the substrate silicon by silicide formation. Thus, a thicker silicide, though favorable at the gate level, is detrimental to shallow junction devices.
U.S. Pat. No. 5,731,239 (Wong et al.) discloses a process for a FET with TiSi.sub.2 S/D contacts 26 and CoSi.sub.x gate contacts 30, see col. 7, lines 4 to 14. A main purpose of the invention is to form two different material silicide layers over (a) the gate and (b) the S/D. This patent uses CMP to remove a second layer of insulator with Si.sub.3 N.sub.4 as a stop layer.
U.S. Pat. No. 5,352,631 (Sitaram et al.) shows a method of forming a FET with a first Metal Silicide (e.g. TiSi.sub.x) S/D contacts (see col. 4, lines 16-35) and second metal silicide (e.g., refractory metal, see col. 5, lines 15-17.) gate contacts. See claim 1. See FIGS. 1 to 5. A main purpose of the patent is to form two different material silicide layers over (a) the gate and (b) the S/D. This patent forms the silicide first, after which the source/drain regions are formed using ion implant. The top layer of the gate contains TiSi.sub.2.
U.S. Pat. No. 5,447,875 (Moslehi) shows a method for forming 2 different composition Silicide layers over the S/D and Gate.
U.S. Pat. No. 5,464,782 (Koh) shows a salicide process using Ti.
U.S. Pat. No. 5,710,438 (Oda et al.) shows a Salicide process using Co.
U.S. Pat. No. 5,208,472 (Su et al.) shows a salicide process using two spacers.
U.S. Pat. No. 5,705,417 (Tseng) shows a salicide process using Ti or Co.
U.S. Pat. No. 5,726,479 (Matsumoto et al.) shows a salicide process on a gate with a large contact area.
U.S. Pat. No. 5,736,461 (Berti et al.) shows a salicide structure with both TiSi.sub.x and CoSi.sub.x on the S/D and gate.